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USB2005 USB2.0 ATA/ATAPI Controller with PD-DRM
PRODUCT FEATURES
Datasheet

Provides support for digital rights management for portable devices (PD-DRM) via Mass Storage Class SCSI Inquiry command as specified by Microsoft for Windows Media Systems (WM-DRM). Reports all media as Removable (HDDs only). 2.5 Volt, Low Power Core Operation 3.3 Volt I/O with 5V input tolerance Supports a low-cost single 3.3V regulator design, by using a 1N4001 diode to provide the 2.5V core voltage (from the 3.3V supply) Complete USB Specification 2.0 Compatibility
-- Includes USB2.0 Transceiver -- A Bi-directional Control and a Bi-directional Bulk Endpoint are provided.
8051 8 bit microprocessor
-- Provides low speed control functions -- 30 Mhz execution speed at 4 cycles per instruction average -- 768 Bytes of internal SRAM for general purpose scratchpad or program execution while re-flashing external ROM
Double Buffered Bulk Endpoint
-- Bi-directional 512 Byte Buffer for Bulk Endpoint -- 64 Byte RX Control Endpoint Buffer -- 64 Byte TX Control Endpoint Buffer
Internal or External Program Memory Interface
-- 48K Byte Internal ROM or optional 64K Byte External Code Space using Flash, SRAM, or EPROM Memory

Complete System Solution for interfacing ATA or ATAPI devices to USB2.0 bus
-- -- -- -- Supports USB Mass Storage Compliant Bootable BIOS Supports ATA6 Drive capacities up to 2048GB True UDMA Mode 4 transfer rates Support for ATAPI Devices:
- CD-ROM - CD-R - CD-RW - DVD - DVD/R/W Support for sharing ATA/ATAPI drive with external microprocessor for file playback in portable media player applications
-- Pin indication of USB bus SUSPEND state -- Control pin to force drive interface high impedance state for drive sharing
On Board 12Mhz Crystal Driver Circuit Internal PLL for 480Mhz USB2.0 Sampling, 30Mhz MCU clock, and 60Mhz ATA clock Supports firmware upgrade via USB bus if "boot block" Flash program memory is used for optional external program memory Optional Serial EEPROM interface for VID/PID/Serial Number Customization 100STQFP Package (12x12x1.4mm body, 14x14mm footprint); green, lead-free package also available
SMSC USB2005
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USB2.0 ATA/ATAPI Controller with PD-DRM Datasheet
ORDER NUMBER(S): USB2005-MN FOR 100 PIN, STQFP PACKAGE USB2005-MV-01 FOR 100 PIN, STQFP PACKAGE (GREEN, LEAD-FREE)
80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123
Copyright (c) 2005 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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Table of Contents
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter 2 Pin Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 5 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 6 Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chapter 7 PD-DRM Usage & Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1 7.2 SCSI Inquiry Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SCSI Inquiry Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2.1 Device Serial Number & Page Length (Bytes 3 & 4...n) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 8 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.1 8.2 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 9 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1 9.2 ATA/ATAPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 USB2.0 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 10 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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List of Figures
Figure 3.1 Figure 4.1 Figure 6.1 Figure 10.1 USB2005 STQFP 100 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 USB2005 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 USB2005 Typical Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 USB2005 100 Pin STQFP Package (12x12x1.4 mm body, 14x14 mm footprint) . . . . . . . . . 21
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List of Tables
Table 1.1 Table 2.1 Table 5.1 Table 5.2 Table 7.1 Table 7.2 Operational Conditions to Electrically Detach USB2005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 USB2005 Pin Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 USB2005 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 USB2005 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SCSI INQUIRY Command Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data Buffer Returned for Device Serial Number Query. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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Chapter 1 General Description
The USB2005 is a USB2.0 Mass Storage Class Peripheral Controller intended for use with standard ATA-5 and -6 hard in media player applications requiring Portable Device - Digital Rights Management (PD-DRM) as specified by Microsoft for Windows Media systems. This includes reporting all media as removable drives and providing the drive serial number to the PC host via a SCSI Inquiry command. The device consists of a USB2.0 PHY and SIE, buffers, Fast 8051 microprocessor with expanded scratchpad and 768 of program SRAM, internal 48 KB program ROM, and an ATA-66 compatible interface. Provisions for optional external Flash Memory up to 64K bytes for program storage is provided. An optional serial EEPROM which can be modified via USB from the host provides unique VID/PID/Serial numbers, as well as optional configuration information. Internal 768 Bytes of scratchpad SRAM are also provided. This internal SRAM can also be used for program storage to implement program upgrade via USB download to external "boot block" Flash program memory, if desired. To facilitate portable media player designs, the ability to electrically detach the USB2005 from the drive under external microprocessor control is provided, as well as an indication to that processor if the USB bus is SUSPENDed when the USB2005 is attached to a USB host. See table below:
Table 1.1 Operational Conditions to Electrically Detach USB2005
OPERATIONAL CONDITION Attached to USB but USB host powered down. ie no VBUS from host PC (IDE interface high impedance) Media player uP forcing USB detach and high impedance of USB2005 IDE interface External uP in media player allows USB connection of USB2005 while attached to USB bus USB BUS STATUS Unpowered X Enumerating GPIO3 INPUT 0 0 1 0 0 Toggle due to optional external SEEPROM data reads 1 0 GPIO1 OUTPUT
Normal USB operation/access to IDE USB2005 attached to USB bus; USB Host in SUSPEND or Safe Removal has occurred via toolbar applet (USB2005 IDE interface high impedance) Media Player detached from USB bus (USB2005 IDE interface high impedance)
Normal Operation SUSPEND
1 X
Unconnected
X
0
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Chapter 2 Pin Table
Table 2.1 USB2005 Pin Table
DISK DRIVE INTERFACE (27 PINS) IDE_D0 IDE_D4 IDE_D8 IDE_D12 IDE_nIOR IDE_DRQ IDE_SA1 IDE_D1 IDE_D5 IDE_D9 IDE_D13 IDE_nIOW IDE_nCS0 IDE_SA2 IDE_D2 IDE_D6 IDE_D10 IDE_D14 IDE_IRQ IDE_nCS1 IORDY IDE_D3 IDE_D7 IDE_D11 IDE_D15 IDE_DACK IDE_SA0
USB INTERFACE (7 PINS) USBD+ RTERM USBDFS+ LOOPFLTR FSRBIAS
MEMORY/IO INTERFACE (28 PINS) MD0 MD4 MA0 MA4 MA8 MA12 nMRD MD1 MD5 MA1 MA5 MA9 MA13 nIOR MISC (15 PINS) ROMEN GPIO4/EE_DIO XTAL1/CLKIN TST_OUT/DBGOUT GPIO1/SUSPEND GPIO5/ATA RESET XTAL2 nTESTEN GPIO2/EE_CS GPIO6/A16 nRESET CLKOUT GPIO3/VBUS GPIO7/EE_CLK nTEST/nDBGSTR MD2 MD6 MA2 MA6 MA10 MA14 nMWR MD3 MD7 MA3 MA7 MA11 MA15 nIOW
POWER, GROUNDS, AND NO CONNECTS (23 PINS)
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Chapter 3 Pin Configuration
ROMEN GPIO1 GPIO2 GPIO3 GND GPIO4 GPIO5 GPIO6 GPIO7 nTEST0 nTEST1 nTEST2 VDDIO IDE_D8 IDE_D7 IDE_D9 VDD IDE_D6 IDE_D10 GND IDE_D5 IDE_D11 IDE_D4 VDDIO IDE_D12 75 RBIAS VDDA FS+ USB+ USBFSRTERM VSSA XTAL1/CLKIN XTAL2 VSSP LOOPFLTR VDDP N.C. N.C. MD7 MD6 MD5 MD4 GND MD3 MD2 MD1 MD0 nRESET 51 IDE_D3 IDE_D13 IDE_D2 GND IDE_D14 IDE_D1 IDE_D15 IDE_D0 VDDIO IDE_DRQ IDE_nIOW IDE_nIOR IORDY GND IDE_DACK IDE_IRQ IDE_SA1 IDE_SA0 VDD IDE_SA2 IDE_nCS0 IDE_nCS1 VDDIO nMWR nMRD 25
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nIOR nIOW VDDIO CLKOUT MA15 MA14 GND MA13 MA12 VDD MA11 MA10 MA9 MA8 VDDIO MA7 MA6 MA5 MA4 N.C. MA3 MA2 MA1 MA0 GND
Figure 3.1 USB2005 STQFP 100 Pin
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Chapter 4 Block Diagram
Auto address generators 512 Bytes EP2 TX/RX Buffer B 512 Bytes EP2 TX/RX Buffer A 64 Bytes EP1RX 64 Bytes EP1TX 64 Bytes EP0RX EP0RX_BC Address 64 Bytes EP0TX
Address MUX
Address Register
Clocked byPhase 0 Clock SIE ( Serial Interface Engine ) 32 bit 15MHz Data Buss
SIE Control Regs USB2.0 PHY ( Transciever )
XDATA 8 bits ( Address and Data busses )
7 pins
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USB2.0 ATA/ATAPI Controller with PD-DRM
Address EP0TX_BC Address
1.25KB SRAM
Data Buss
EP1TX_BC EP1RX_BC
Address Address
32 Bit
60MHz
RAMWR_A/B
Address
Latch phase 0
Latch phase 1
Latch phase 2
Future phase 3 Clocked byPhase 2 Clock
RAMRD_A/B
Address
Data @ 32 bit 15MHz ATA-66 Interface ATA/ATAPI Drive
Configuration and Control
GPIO
7 pins
Clock Generation Interrupt Controller Osc
768 Byte Program/Scratchpad SRAM
48KB ROM
ROMEN
MEM/IO Bus OPTIONAL External PHY CLOCKOUT XTAL
29pins
Program Memory/ IO Bus
FAST 8051 CPU CORE Debug Serial 2 wire ( Data/Strobe) 2 pins
12 MHz
Clocked byPhase 1 Clock
Figure 4.1 USB2005 Block Diagram
USB2.0 ATA/ATAPI Controller with PD-DRM Datasheet
Chapter 5 Pin Description
Table 5.1 USB2005 Pin Descriptions
DISK DRIVE INTERFACE IDE DMA Request IDE IO Read Strobe IDE Register Address 1 IDE Register Address 0 IDE Register Address 2 IDE Data IDE IO Write Strobe IDE DMA Acknowledge IDE Interrupt Request IDE Data IDE Data IDE Chip Select 0 IDE Chip Select 1 0 IDE Data IO Ready IDE_DRQ IDE_nIOR IDE_SA1 IDE_SA0 IDE_SA2 IDE_D15 IDE_nIOW IDE_nDACK IDE_IRQ IDE_D13 IDE_D14 IDE_nCS0 IDE_nCS1 IDE_D[0:12] IORDY IS O20 O20 O20 O20 IO20 O20 O20 IS IO20 IO20 O20 O20 IO20 I USB INTERFACE USB Bus Data USB Transceiver Filter USB Transceiver Bias Termination Resistor USBUSB+ LOOPFLTR IO-U These pins connect to the USB bus data signals. This pin provides the ability to supplement the internal filtering of the transceiver with an external network, if required. A 9.09 Kohm precision resistor is attached from ground to this pin to set the transceiver's internal bias currents. A precision 1.5Kohm precision resistor is attached to this pin from a 3.3V supply.
10 SMSC USB2005
This pin is the active high DMA request from the ATA/ATAPI interface. This pin is the active low read signal for the interface. This pin is the register select address bit 1 signal for the ATA/ATAPI interface. This pin is the register select address bit 0 signal for the ATA/ATAPI interface. This pin is the register select address bit 2 signal for the ATA/ATAPI interface. This pin is the bi-directional data bus bit 15 signal for the ATA/ATAPI interface. This pin is active low write signal for the ATA/ATAPI interface. This pin is the active low DMA acknowledge signal for the ATA/ATAPI interface. This pin is the active high interrupt request signal for the ATA/ATAPI interface. This pin is the bi-directional data bus bit 13 signal for the ATA/ATAPI interface. This pin is the bi-directional data bus bit 14 signal for the ATA/ATAPI interface. This pin is the active low chip select 0 signal for the ATA/ATAPI interface. This pin is the active low select 1 signal for the ATA/ATAPI interface. These pins are bits 0-12 of the ATA/ATAPI bidirectional data bus. This pin is the active high IORDY signal from the IDE drive.
RBIAS
RTERM
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Table 5.1 USB2005 Pin Descriptions (continued)
Full Speed USB Data FSFS+ IO-U These pins connect to the USB- and USB+ pins through 31.6 ohm series resistors.
MEMORY/IO INTERFACE Memory Data Bus MD[7:0] IO12PU When ROMEN=0, these signals are used to transfer data between the internal CPU and the external program memory. When ROMEN=1, a weak internal pull up is activated to prevent these pins from floating. These signals address memory locations within the external memory. Program Memory Write; active low Program Memory Read; active low XDATA space Read; active low XDATA space Write; active low MISC Crystal Input/External Clock Input Crystal Output XTAL1/ CLKIN ICLKx 12Mhz Crystal or external clock input. This pin can be connected to one terminal of the crystal or can be connected to an external 12Mhz clock when a crystal is not used. 12Mhz Crystal This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN. It may not be used to drive any external circuitry other than the crystal circuit. This pin produces a 30Mhz clock signal independent of the processor clock divider. It is held inactive and low whenever the internal processor clock is stopped or is being obtained from the ring oscillator. When left unconnected or tied high, the USB97C202 uses the internal ROM for program execution. When tied low, an external program memory should be connected to the memory/data bus. The state of this pin latched internally on the rising edge of nRESET. These general purpose pins may be used either as inputs, edge sensitive interrupt inputs, or outputs. When using internal ROM mode, these pins have the following assignments: GPIO1: USB SUSPEND Indicator; active high GPIO2: Optional Serial EEPROM (93LC56 type) Chip Select GPIO3: USB VBUS Detect Input (can be used to force the IDE interface to high impedance state) GPIO4: Optional Serial EEPROM Data In/Out GPIO5: ATA Drive Reset GPIO6: A16 control line for external program Flash memory when using firmware upgrade capability (external ROM operation only) GPIO7: Optional Serial EEPROM Clock output
Memory Address Bus Memory Write Strobe Memory Read Strobe IO Read Strobe IO Write Strobe
MA[15:0] nMWR nMRD nIOR nIOW
O12 O12 O12 O12 O12
XTAL2
OCLKx
Clock Output
CLKOUT
O8
Internal ROM Enable
ROMEN
IP
General Purpose I/O
GPIO[1:7]
IO20
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Table 5.1 USB2005 Pin Descriptions (continued)
RESET input nRESET IS This active low signal is used by the system to reset the chip. The active low pulse should be at least 100ns wide. These signals are used for testing the chip. User should normally leave them unconnected. For board continuity testing, all pads (except RBIAS, FSDP, USBDP, USBDM, FSDM, RTERM, XTAL1, XTAL2, LOOPFLTR and nTEST[0:2]) are included in an XNOR chain which is enabled by pulling nTEST2 low. nIOR is the output of the chain (the chain begins at pin 2) and will reflect the toggling of a signal on each pin. Circuit board continuity of the pin solder connections after assembly can be checked in this manner
Test input
nTest[0:2]
IP
POWER, GROUNDS, AND NO CONNECTS VDD VDDIO VDDP VSSP VDDA VSSA GND NC +2.5V Core power +3.3V I/O power +2.5 Analog power Analog Ground Reference +3.3V Analog power Analog Ground Reference Ground Reference No Connect. These pins should not be connected externally.
5.1
Buffer Type Descriptions
Table 5.2 USB2005 Buffer Type Descriptions
BUFFER I IS IP IO8 O8 O12 IO12PU IO12 IO20 O20 O20PU Input Input with Schmitt trigger Input with weak pull-up Input/Output with 8 mA drive Output with 8mA drive Output with 12mA drive Input/Output with 12 ma drive and controlled weak pull up Input/Output with 12 ma drive Input/output with 20mA drive Output with 20mA drive Output with 20mA drive and weak pullup DESCRIPTION
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Table 5.2 USB2005 Buffer Type Descriptions (continued)
BUFFER ICLKx OCLKx I/O-U XTAL clock input XTAL clock output Defined in USB specification DESCRIPTION
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Chapter 6 Typical Application
USB power input
3.3V Battery supply to USB2005
Media Player
USB Bus Status 1N4001 HDD Interface Control
3.3V Regulator
3.3V
2.5V
USB
USB2005 Micro HDD
Optional Configuration SEEPROM
Optional External Program Memory
Figure 6.1 USB2005 Typical Application
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Chapter 7 PD-DRM Usage & Description
The USB2005 is a USB2.0 Mass Storage Class Peripheral Controller intended for use with standard ATA-5 and -6 hard disk drives in media player applications requiring Portable Device - Digital Rights Management (PD-DRM) as specified by Microsoft for Windows Media systems. This includes reporting all media as removable drives and providing the drive serial number to the PC host via the SCSI Inquiry command.
7.1
SCSI Inquiry Command
In accordance with the SCSI-2 specification the INQUIRY command has the format shown in Table 7.1, "SCSI INQUIRY Command Block"
Table 7.1 SCSI INQUIRY Command Block
BIT 7 Byte 0: Operation Code Byte 1: Logical Unit Number Byte 2: Parameters 1 Byte 3: Parameters 2 Byte 4: Parameters 3 Byte 5: Control Field 12h LUN Page Code Reserved Allocation Length Vendor Specific Reserved Flag Link Reserved EVPD BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
When performing a device serial number query, the following fields must be programmed as follows: EVPD = 1, and Page Code = 80h
7.2
SCSI Inquiry Response
In accordance with the SCSI-2 specification the response to INQUIRY command has the format shown in Table 7.2, "Data Buffer Returned for Device Serial Number Query".
Table 7.2 Data Buffer Returned for Device Serial Number Query
BYTE # 0 1 2 3 4 n BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Peripheral Qualifier Page Code (80h) Reserved Page Length (n-3) Device serial number
Device Type Code
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7.2.1
Device Serial Number & Page Length (Bytes 3 & 4...n)
In response to a SCSI INQUIRY Command, the USB2005 firmware will read the "Device Identify Information" of an IDE drive. The Device Serial Number is created by removing all NULL code (00h) and BLANK code (20h) characters from the "Device Identify Information" response. The Device Serial Number is reported in Byte 4...n (see Table 7.2). The number of characters of the Device Serial Number will be reported as the Page Length (Byte 3) see Table 7.2. As a simple example, If the Device Identify Information of an IDE drive is 713 740, then the USB2005 will return 713740 as the Device Serial Number with a Page Length of 6.
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Chapter 8 DC Parameters
8.1 Maximum Guaranteed Ratings
Operating Temperature Range ............................................................................................0oC to +70oC Storage Temperature Range............................................................................................. -55o to +150oC Lead Temperature Range (soldering, 10 seconds) ...................................................................... +325oC Positive Voltage on any pin, with respect to Ground ........................................................................ 5.5V Negative Voltage on any pin, with respect to Ground ..................................................................... -0.3V Maximum VDDA, VDDIO..................................................................................................................... +4.0V Maximum VDD, VDDP ........................................................................................................................ +3.0V *Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used.
8.2
DC Electrical Characteristics
(TA = 0C - 70C, VDDIO, VDDA = +3.3 V 10%, VDD, VDDP = +2.5 V 10%,) PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS
I Type Input Buffer Low Input Level High Input Level ICLK Input Buffer Low Input Level High Input Level Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage IIL IIH -10 -10 +10 +10 A A VIN = 0 VIN = VDDIO VILCK VIHCK 2.2 0.4 V V VILI VIHI 2.0 0.8 V V TTL Levels
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PARAMETER O8 Type Buffer Low Output Level
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VOL
0.4
V
IOL = 8 mA @ VDDIO = 3.3V IOH = -4mA @ VDDIO = 3.3V VIN = 0 to VDDIO (Note 8.1)
High Output Level
VOH
2.4
V
Output Leakage I/O8 Type Buffer Low Output Level
IOL
-10
+10
A
VOL
0.4
V
IOL = 8 mA @ VDDIO = 3.3V IOH = -4 mA @ VDDIO = 3.3V VIN = 0 to VDDIO (Note 8.1, 8.2)
High Output Level
VOH
2.4
V
Output Leakage I/O12 Type Buffer Low Output Level
IOL
-10
+10
A
VOL
0.4
V
IOL = 12 mA @ VDDIO = 3.3V IOH = -6mA @ VDDIO = 3.3V VIN = 0 to VDDIO (Note 8.1, 8.2)
High Output Level
VOH
2.4
V
Output Leakage I/O20 Type Buffer Low Output Level
IOL
-10
+10
A
VOL
0.4
V
IOL = 20 mA @ VDDIO = 3.3V IOH = -5 mA @ VDDIO = 3.3V VIN = 0 to VDDIO (Note 8.1, 8.2)
High Output Level
VOH
2.4
V
Output Leakage IO-U Supply Current Unconfigured Supply Current Active Note 8.1 Note 8.2
IOL
-10
+10
A
ICCINIT ICC
65 85 85 120
mA mA mA mA
VDDIO, VDDA VDD, VDDP VDDIO, VDDA VDD, VDDP
Output leakage is measured with the current pins in high impedance. Output leakage is valid only on pins without internal weak pull ups or pull downs.
Revision 0.2 (06-07-05)
DATASHEET
18
SMSC USB2005
USB2.0 ATA/ATAPI Controller with PD-DRM Datasheet
CAPACITANCE TA = 25C; fc = 1MHz; VDD = 2.5V LIMITS PARAMETER Clock Input Capacitance SYMBOL CIN MIN TYP MAX 20 UNIT pF TEST CONDITION All pins except USB pins (and pins under test tied to AC ground)
Input Capacitance Output Capacitance
CIN COUT
10 20
pF pF
SMSC USB2005
DATASHEET
19
Revision 0.2 (06-07-05)
USB2.0 ATA/ATAPI Controller with PD-DRM Datasheet
Chapter 9 AC Specifications
9.1 ATA/ATAPI
The USB2005 conforms to all timing diagrams and specifications for ATAPI-5 as set forth in the T13/1321D Revision 3 NCITS specification. Please refer to this specification for more information.
9.2
USB2.0 Timing
The USB2005 conforms to all timing diagrams and specifications for USB peripheral silicon building blocks as set forth in the USB-IF USB2.0 specification. Please refer to this specification for more information.
Revision 0.2 (06-07-05)
DATASHEET
20
SMSC USB2005
Chapter 10 Package Outline
REVISION HISTORY
REVISION -
Revision 0.2 (06-07-05) 21 DATASHEET SMSC USB2005
Datasheet
USB2.0 ATA/ATAPI Controller with PD-DRM
DESCRIPTION
SEE SPEC FRONT PAGE FOR REVISION HISTORY
DATE
-
RELEASED BY
-
5
D D1 3
R1 R2 0.25
E1/4
GAUGE PLANE
0-7
3 E1 e
D1/4
4 b 2 E
L L1
DETAIL "A"
TOP VIEW
SEE DETAIL "A" A2 c A1 ccc C
C A
SEATING PLANE
SIDE VIEW
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETER. 2. TRUE POSITION SPREAD TOLERANCE OF EACH LEAD IS 0.035mm MAXIMUM. 3. DIMENSIONS "D1" AND "E1" DO NOT INCLUDE MOLD PROTRUSIONS. MAXIMUM ALLOWED PROTRUSION IS 0.25 mm PER SIDE. 4. DIMENSION "L" IS MEASURED AT THE GAUGE PLANE, 0.25mm ABOVE THE SEATING PLANE. 5. DETAILS ON PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND TOLERANCES ARE: DECIMAL 0.1 X.X X.XX 0.05 X.XXX 0.025 ANGULAR 1 THIRD ANGLE PROJECTION 80 ARKAY DRIVE HAUPPAUGE, NY 11788 USA
INTERPRET DIM AND TOL PER ASME Y14.5M - 1994 MATERIAL
TITLE NAME DRAWN DATE
3-D VIEW
FINISH
S.K.ILIEV
CHECKED
12/17/04 12/17/04
PACKAGE OUTLINE 100 STQFP-12x12x1.4mm BODY-0.4mm PITCH
DWG NUMBER REV
PRINT WITH "SCALE TO FIT" DO NOT SCALE DRAWING
S.K.ILIEV
APPROVED
MO-100-STQFP-12x12x1.4
SCALE STD COMPLIANCE SHEET
C 1 OF 1
S.K.ILIEV
12/17/04
1:1
JEDEC: MS-026 (D)
Figure 10.1 USB2005 100 Pin STQFP Package (12x12x1.4 mm body, 14x14 mm footprint)

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